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Hennessy / Patterson

Computer Architecture

A Quantitative Approach

Medium: Buch
ISBN: 978-0-12-383872-8
Verlag: William Andrew Publishing
Erscheinungstermin: 25.10.2011
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Computer Architecture: A Quantitative Approach, Fifth Edition, explores the ways that software and technology in the cloud are accessed by digital media, such as cell phones, computers, tablets, and other mobile devices. The book, which became a part of Intel's 2012 recommended reading list for developers, covers the revolution of mobile computing. It also highlights the two most important factors in architecture today: parallelism and memory hierarchy.

This fully updated edition is comprised of six chapters that follow a consistent framework: explanation of the ideas in each chapter; a crosscutting issues section, which presents how the concepts covered in one chapter connect with those given in other chapters; a putting it all together section that links these concepts by discussing how they are applied in real machine; and detailed examples of misunderstandings and architectural traps commonly encountered by developers and architects. Formulas for energy, static and dynamic power, integrated circuit costs, reliability, and availability are included. The book also covers virtual machines, SRAM and DRAM technologies, and new material on Flash memory. Other topics include the exploitation of instruction-level parallelism in high-performance processors, superscalar execution, dynamic scheduling and multithreading, vector architectures, multicore processors, and warehouse-scale computers (WSCs). There are updated case studies and completely new exercises. Additional reference appendices are available online.

This book will be a valuable reference for computer architects, programmers, application developers, compiler and system software developers, computer system designers and application developers.


Produkteigenschaften


  • Artikelnummer: 9780123838728
  • Medium: Buch
  • ISBN: 978-0-12-383872-8
  • Verlag: William Andrew Publishing
  • Erscheinungstermin: 25.10.2011
  • Sprache(n): Englisch
  • Auflage: 5. Auflage 2011
  • Produktform: Kartoniert
  • Gewicht: 1678 g
  • Seiten: 856
  • Format (B x H): 191 x 235 mm
  • Ausgabetyp: Kein, Unbekannt
  • Vorauflage: 978-0-12-370490-0
Autoren/Hrsg.

Autoren

ACM named John L. Hennessy a recipient of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry. John L. Hennessy is a Professor of Electrical Engineering and Computer Science at Stanford University, where he has been a member of the faculty since 1977 and was, from 2000 to 2016, its tenth President. Prof. Hennessy is a Fellow of the IEEE and ACM; a member of the National Academy of Engineering, the National Academy of Science, and the American Philosophical Society; and a Fellow of the American Academy of Arts and Sciences. Among his many awards are the 2001 Eckert-Mauchly Award for his contributions to RISC technology, the 2001 Seymour Cray Computer Engineering Award, and the 2000 John von Neumann Award, which he shared with David Patterson. He has also received seven honorary doctorates.

David Patterson is the Pardee Professor of Computer Science, Emeritus at the University of California at Berkeley, which he joined after graduating from UCLA in 1977.His teaching has been honored by the Distinguished Teaching Award from the University of California, the Karlstrom Award from ACM, and the Mulligan Education Medal and Undergraduate Teaching Award from IEEE. Prof. Patterson received the IEEE Technical Achievement Award and the ACM Eckert-Mauchly Award for contributions to RISC, and he shared the IEEE Johnson Information Storage Award for contributions to RAID. He also shared the IEEE John von Neumann Medal and the C & C Prize with John Hennessy. Like his co-author, Prof. Patterson is a Fellow of the American Academy of Arts and Sciences, the Computer History Museum, ACM, and IEEE, and he was elected to the National Academy of Engineering, the National Academy of Sciences, and the Silicon Valley Engineering Hall of Fame. He served on the Information Technology Advisory Committee to the U.S. President, as chair of the CS division in the Berkeley EECS department, as chair of the Computing Research Association, and as President of ACM. This record led to Distinguished Service Awards from ACM, CRA, and SIGARCH.

Printed TextChap 1: Fundamentals of Quantitative Design and AnalysisChap 2: Memory Hierarchy DesignChap 3: Instruction-Level Parallelism and Its ExploitationChap 4: Data-Level Parallelism in Vector, SIMD, and GPU ArchitecturesChap 5: Multiprocessors and Thread-Level ParallelismChap 6: The Warehouse-Scale ComputerApp A: Instruction Set PrinciplesApp B: Review of Memory HierarchyApp C: Pipelining: Basic and Intermediate Concepts

OnlineApp D: Storage SystemsApp E: Embedded SystemsApp F: Interconnection NetworksApp G: Vector ProcessorsApp H: Hardware and Software for VLIW and EPICApp I: Large-Scale Multiprocessors and Scientific ApplicationsApp J: Computer Arithmetic App K: Survey of Instruction Set ArchitecturesApp L: Historical Perspectives