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This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
Produkteigenschaften
- Artikelnummer: 9789811093210
- Medium: Buch
- ISBN: 978-981-10-9321-0
- Verlag: Springer
- Erscheinungstermin: 12.05.2018
- Sprache(n): Englisch
- Auflage: Softcover Nachdruck of the original 1. Auflage 2018
- Serie: Computer Architecture and Design Methodologies
- Produktform: Kartoniert, Paperback
- Gewicht: 3401 g
- Seiten: 197
- Format (B x H x T): 155 x 235 x 13 mm
- Ausgabetyp: Kein, Unbekannt