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Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
Produkteigenschaften
- Artikelnummer: 9789048182008
- Medium: Buch
- ISBN: 978-90-481-8200-8
- Verlag: Springer
- Erscheinungstermin: 28.10.2010
- Sprache(n): Englisch
- Auflage: 1. Auflage 2010
- Serie: Lecture Notes in Electrical Engineering
- Produktform: Kartoniert, Paperback
- Gewicht: 324 g
- Seiten: 198
- Format (B x H x T): 155 x 235 x 12 mm
- Ausgabetyp: Kein, Unbekannt