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A project’s functional verification testplan is the specification for the verification process. Developing this testplan usually involves the entire engineering team (architects, designers, and verification engineers). This book presents formal testplanning guidelines with examples focused on creating assertion-based verification IP. This is the first book published on this subject. It demonstrates a systematic process for formal specification and formal testplanning, and also demonstrates effective use of assertions languages beyond the traditional language construct discussions. Note that there many books published on assertion languages (such as SystemVerilog assertions and PSL). Yet, none of them discuss the important process of testplanning and using these languages to create verification IP.
Produkteigenschaften
- Artikelnummer: 9780387366418
- Medium: Buch
- ISBN: 978-0-387-36641-8
- Verlag: Springer US
- Erscheinungstermin: 26.11.2007
- Sprache(n): Englisch
- Auflage: 2008
- Serie: Integrated Circuits and Systems
- Produktform: Gebunden
- Gewicht: 670 g
- Seiten: 318
- Format (B x H x T): 160 x 241 x 23 mm
- Ausgabetyp: Kein, Unbekannt